1. Field of the Invention
The present invention relates to an image data storing method and image data storing device applicable for various display devices such as liquid crystal displays, and particularly to those which can achieve downsizing, and are preferably applied to two-dimensional or three-dimensional graphics.
2. Description of Related Art
As is well known, a screen of a liquid crystal display consists of a lot of pixels arrayed in a matrix. Such a liquid crystal display generates a picture by controlling the transmittivity (reflectivity) of all the pixels by sequentially applying voltages corresponding to pixel data to liquid crystal elements mounted for individual pixels.
An image data storing device used in such a display device adopts various design ideas because it is necessary for a great number of pixel data to be read within a certain limited time to prevent screen flickering.
FIG. 6 is a block diagram showing a layout of an image data storing integrated circuit considering such an image read time. In FIG. 6, reference numerals 51, 52, 53, 54 and 55 each designate a physical bank, a repetition unit of a memory area in the memory layout; 8s designate memory buses, each of which has a bus width of m corresponding to the pixel data, and p (=4, in FIG. 6) of which are each connected to the physical banks 51, 52, 53, 54 and 55; and 61, 62, 63 and 64 each designate a memory group, each of which corresponds to one pixel, and consists of a plurality of memory elements connected to one of the memory buses 8. Reference numerals 71, 72, 73 and 74 each designate a group of n address decoders, each of which is provided for one of the memory groups for selecting a memory element for outputting one pixel data. Thus, the total number of address decoders amounts to p.times.n. The reference numeral 9 designates a selector for selecting n (=5 in FIG. 6) memory buses 8 from among the plurality of memory buses 8 to output the image data on the selected memory buses 8. Incidentally, the bus width (the number of lines of each bus) m of each memory bus 8 is determined in accordance with the number of gray levels of a pixel, and when the number of bits needed for the pixel is m bits, the bus width is also set at m in general.
Next, the image data storing method of the conventional image data storing integrated circuit will be described.
In the foregoing image data storing integrated circuit, pixels constituting a display picture are divided into pixel groups, each of which consists of p.times.n pixels. Then, the pixel data (1,1), (1,2), . . . , and (1,n) in the first row are stored in the (1,1) memory group 61, (1,2) memory group 61, . . . , and (1,n) memory group 61, respectively. Likewise, the pixel data (2,1), (2,2), . . . , and (2,n) in the second row are stored in the memory group 62, followed by storing the third row and onward in the same manner. Finally, the pixel data (p,1), (p,2), . . . , and (p,n) in the p-th row are stored in the memory group 64.
Next, the read operation of the conventional device will be described.
In a common image display mode, the pixel data corresponding to the pixels in the first row are successively read on an every n pixel basis by actuating the n address decoders 71, . . . , 71 while setting the selector 9 such that it outputs the data of the memory groups 61, . . . , 61 in the first row, thereby completing the first row. Likewise, the pixel data corresponding to the pixels in the second row are successively read on an every n pixel basis by actuating the n address decoders 72, . . . , 72 while setting the selector 9 such that it outputs the data of the memory groups 62, . . . , 62 in the second row, thereby completing the second row. Thus, all the pixel data of the following rows are read one after the other.
According to the image data storing integrated circuit, since the pixel data can be read in groups of n pixels, the time taken to display a picture is reduced by a factor of n. This enables the pixel data to be read in a time that can prevent the flickering of the picture.
In another operation mode of the image data storing integrated circuit, in which 3-D (three-dimensional) graphics or the like are carried out, pixel data are sometimes rewritten column by column at a location in which a displayed picture changes. In such a case, the p (=4) pixel data in each column can be read by actuating the four address decoders 71, 72, 73 and 74 corresponding to the physical bank 51 (52, 53, 54 or 55), after setting the selector 9 such that it outputs the pixel data in the physical bank 51 (52, 53, 54 or 55).
The conventional image data storing integrated circuit with the foregoing configuration must possess p sets of memory buses for each physical bank. As a result, the number of lines needed for reading the pixel data from each of the physical banks becomes m.times.p, amounting to m.times.n.times.p lines for the entire memory. This presents a problem of hindering downsizing of the memory when handling a large scale, high gray level display image.